The invention presented herein relates to a microprocessor controlled laser beam printer using a writing duty cycle of less than 50% and having a single random access memory (RAM) for storage of font information for the laser output control and storage of information for the microprocessor and, in particular, to circuitry for such a printer for switching between two clock sources for addressing the RAM, one clock source for accessing the font information portion in the RAM and a second clock source for accessing the microprocessor information portion in the RAM.
Known laser beam printers use two large memory systems. The first holds the page information to be printed. This is necessary since printing a page cannot begin until the entire page has been received. Moreover, more efficient use of time results if a second page can be inputted while the printing of the first page is still going on. Still further, it is desirable that a multiple page report be stored within the printer so that multiple sets can be printed without need for retransmission.
The second memory holds font information. This information must be "looked up" every time a character is printed, and the quantity of the information depends on the number of fonts to be printed on a job, the size of the character boxes, and the number of characters in a font.
It is possible to combine these memories in a single random access memory (RAM). During a printing portion of a print cycle, the RAM must be totally dedicated to the providing of font information and must be provided at such a speed that the process cannot be microprocessor controlled but must be hardware controlled. However, during the non-printing portion of a print cycle font information is not needed so the RAM can be accessed by the microprocessor as required. The hardware for accessing font information requires a clock generator, the output of which can be used to provide the Row Address Strobe (RAS) with the microprocessor requiring a separate clock generator for accessing information in the RAM for the microprocessor with such clock generator used to provide the Row Address Strobe (RAS). A problem is presented with respect to switching from one clock generator to the other clock generator in that the RAM is intolerant of any imperfect RAS clock cycle. Data is lost if a clock cycle used for a Row Address Strobe is shortened which can occur when a change from one clock generator to the other is implemented causing great problems even if such occurrence is only once every 10,000,000 cycles.